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sdram
- verilog HDL语言，SDRAM驱动程序，基于FPGA，例子程序-verilog HDL languages, the driver, based on FPGA, an example program
sdram
- 文件中包含Sdram的Verilog程序以及很全的Sdram的资料-Sdram the Verilog file contains procedures and information are all of Sdram
sdr_verilog_lattice
- Verilog控制SDRAM-Verilog control SDRAM
source
- 本源码是 基于VERILOG的SDRAM的开发与实现 并能实现 刷新，预充电，突发长度为8字节等功能 已验证，可用-The source is based on the SDRAM VERILOG development and implementation and to achieve refresh, precharge, a burst length of 8 bytes and other functions have been verified, the available
sdram
- 使用VERILOG访问SRAM的程序，有需要的可以拿来借鉴-SRAM using VERILOG access procedures can be used in need of reference
sdr_sdram
- sdram控制器，verilog语言写的-sdram controller, verilog language to write
X-HDL
- 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
SDR_SDRAM_IP
- SDR SDRAM 控制器，Altera官网重要资料。内涵说明文档，和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
83399055ref-sdr-sdram-verilog
- Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our hod for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences,
4port-sdram
- 4端口SDRAM控制器verilog程序-4-port SDRAM controller with verilog
UART_DMA
- 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
Verilog_module
- micron 1G内存条verilog模型，对应具体信号为MT8HTF12864HZ-800，内存颗粒为MT47H128M8CF-25-micron 1G DDR2 SDRAM verilog module
tut_DE2_sdram_verilog
- DE2 sdram 的verilog 教学材料-tut_DE2 sdram verilog.
sdram
- 在ISE环境中，利用verilog语言编写的SDRAM的控制，已经通过功能仿真，其中PLL部分并没有加入，使用时可以自行加入PLL模块。-Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
SDRAM_verilog-serial-port
- FPGA对sdramd的操作，verilog语言设计！-FPGA SDRAM verilog
sdram-ctrl
- FPGA sdram 全页模式控制，用verilog语言写的，非常的精简，控制方便-FPGA sdram full-page mode control, written in verilog language is compact, easy to control
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
SDRAM
- 在nios环境下，结合verilog语言开发，功能是往SDRAM里面写0-99并打印出来-Nios environment, combined with the verilog language development function is to write to the SDRAM inside 0-99 and print out
sdram_mdl
- SDRAM的verilog程序控制模块，希望对大家有帮助-SDRAM verilog program control module, we want to help